Created by: joshua-warburton
i#3044 AArch64 SVE codec: Add support for predicate modes in the IR
This patch adds two new flags to the opnd structure for the use of predicate registers. In AArch64 SVE predicate registers can be zeroing or merging or neither, represented in assembly by register qualifiers /M, /Z or no qualifier. The change assigns a flag to each of these which can be set by instantiating a predicate register via opnd_create_predicate_reg() or opnd_create_reg() depending on wether the zero/merge qualifier is required. Predicate registers can also be manipulated like regular registers and not be zeroing or merging, so the traditional way of creating registers is sill supported for predicate registers.
The mode of the predicate registers is rendered in IR by postfixing the predicate register with either /m or /z as in assembly.
This patch also adds the appropriate macros, tests and codec entries to encode the following variants:
ADD <Zdn>.<Ts>, <Pg>/M, <Zdn>.<Ts>, <Zm>.<Ts>
ADD <Zdn>.<Ts>, <Zdn>.<Ts>, #<imm>, <shift>
ADD <Zd>.<Ts>, <Zn>.<Ts>, <Zm>.<Ts>
PTEST <Pg>, <Pn>.B
CPY <Zd>.<Ts>, <Pg>/Z, #<imm>, <shift>issues: #3044