Adds missing required-1 bits in the ARM encoding table entries for OP_blx, OP_bx, and OP_bxj. Without the bits, some hardware still accepts the instructions (which is why we did not notice the problem before), but they are technically unsound, and QEMU thinks they are invalid, breaking some of our tests under QEMU.
Tested on QEMU with the forthcoming #2414 drwrap-drreg-test, and directly with several other decoders: Prior encoding for "blx r11": :1:1: warning: invalid instruction encoding 0x3b 0x00 0x20 0xe1 ^ llvm-mc: e120003b capstone: e120003b <INVALID: errcode 0> bfd: e120003b ; instruction: 0xe120003b New encoding: $ disasm_a32 e12fff3b llvm-mc: e12fff3b blx r11 capstone: e12fff3b blx r11 bfd: e12fff3b blx fp
Setting up more external-decoder testing is beyond the scope of this fix: #1686 (closed) covers that.
Issue: #4719, #1686 (closed), #2414