drcachesim used to support only power-of-2 associativity even though it's not uncommon for L1 caches to be 3-way, 5-way, or sometimes 24-way for larger caches. Most changes were in option validation and related messages. The use of assoc_bits_ was removed. Shifts and masks were replaced by multiplication (as cheap as shifting, on modern CPUs) and a test. There are no division or modulo operators on the speed path.
This also seemed like a good opportunity to change the misnamed blocks_per_set_ variable to blocks_per_way_ (blocks per set is the same as associativity).
Reworked pull request to fix clang-format issues.