Fixes alignment, size and memref type for address range zeroed using DC ZVA operation on AArch64.
Adds traced processor's cache line size to header of offline raw traces. Using this, during offline trace post-processing, back-align the memory address in DC ZVA and mark the operation as a cache line sized store. This is a workaround for offline traces, and doesn't help in correctness of DC ZVA representation in online traces.
Adds the cache line size as a new marker type in final offline and online traces. For old raw traces without cache line size in header, the present processor's cache line size is used as default during raw2trace.
Repurposes burst_flush_aarch64 to test AArch64 SYS operations in general, and renames it to burst_aarch64_sys. Adds an offline trace analyser test to verify DC ZVA fixes and new marker.
Adds new check to trace invariant test that verifies presence of cache line size marker in online traces.
Updates offline trace for tool.drcacheoff.altbindir test to add cache line size in header.
Issue: #4400