Adds a "dmb ish" barrier prior to the "ldrex..strex" loops in the atomics used to implement mutexes and other operations on 32-bit ARM where we need release-acquire semantics.
Issue: #3956 (closed)
Adds a "dmb ish" barrier prior to the "ldrex..strex" loops in the atomics used to implement mutexes and other operations on 32-bit ARM where we need release-acquire semantics.
Issue: #3956 (closed)