Created by: fhahn
This adds encoding and decoding support the scalar and vector versions of FADD. The patterns are auto-generated using the publicly available ISA spec from https://alastairreid.github.io/ARM-v8a-xml-release/.
For the scalar versions, the H,S and D registers are used to generate the correct encoding. For the vector versions, the newly added V64 register is used for 64 bit wide vector operands and Q for 128 bit wide vectors. We can re-use Q, as no scalar version of FP instructions should use Q registers. But it might be better to add a V128 register class for 128 bit wide vectors.
The element size for single/double is encoded as the fsz operand. Without fsz operand, fp16 is assumed (added in Arm v8.2).
Issue: #2626