Extend drcachesim configurability: support SMT/HT with multiple cores per cache; support NUCA with non-power-of-2 cache sizes

The drcachesim configuration file supports a lot of flexibility in specifying the cache layout to simulate, but it is missing two key features I have run into recently:

• Support multiple cores per cache. Today a cache can only belong to a single core. This makes it impossible to simulate SMT/HT where 2 or more hardware threads share caches.

• Support non-power-of-2 cache sizes. With NUCA LLC it is not uncommon to have non-power-of-2 LLC cache sizes.