drcachesim.delay-simple and drcachesim.invariants fail on ARM
Created by: fhahn
There are 2 drcachesim test failures on ARM: drcachesim.delay-simple and drcachesim.invariants
The new AArch32 precommit builder shows the logs for the failing tests: http://jenkins.fhahn.com:8080/job/DynamoRIO-AArch32-Precommit/5/console
136/153 Test #133: code_api|tool.drcachesim.delay-simple ...........***Failed Required regular expression not found.Regex=[^Hit delay threshold: enabling tracing.
Exiting process after ~1.... references.
---- <application exited with code 0> ----
Cache simulation results:
Core #0 \(1 thread\(s\)\)
L1I stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
.* Miss rate: *[0-9,\.]*%
L1D stats:
Hits: *[0-9,\.]*
Misses: *[0-9,\.]*.
.* Miss rate: *[0-9,\.]*%
Core #1 \(0 thread\(s\)\)
Core #2 \(0 thread\(s\)\)
Core #3 \(0 thread\(s\)\)
LL stats:
Hits: *[0-9,\.]*.
Misses: *[0-9,\.]*..
.* Local miss rate: *[0-9,\.]*%
Child hits: *[0-9,\.]*.
Total miss rate: *[0-9,\.]*%
$
] 3.87 sec
Hit delay threshold: enabling tracing.
Exiting process after ~6104240175158657024 references.
---- <application exited with code 0> ----
Cache simulation results:
Core #0 (1 thread(s))
L1I stats:
Hits: 10,239
Misses: 48
Miss rate: 0.47%
L1D stats:
Hits: 3,447
Misses: 114
Prefetch hits: 18
Prefetch misses: 96
Miss rate: 3.20%
Core #1 (0 thread(s))
Core #2 (0 thread(s))
Core #3 (0 thread(s))
LL stats:
Hits: 2
Misses: 160
Prefetch hits: 1
Prefetch misses: 95
Local miss rate: 98.77%
Child hits: 13,704
Total miss rate: 1.15%
152/153 Test #141: code_api|tool.drcachesim.invariants .............***Failed Required regular expression not found.Regex=[^.*
Trace invariant checks passed
$
] 90.03 sec